Gameboy Development Forum
Discussion about software development for the old-school Gameboys, ranging from the "Gray brick" to Gameboy Color
(Launched in 2008)
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#1 2015-12-03 16:47:26
- LeiTo
- New member
- Registered: 2015-12-03
- Posts: 1
MBC1
Guys, can anyone give me a circuit diagram of MBC1?
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#2 2015-12-03 17:33:40
- Tauwasser
- Member
- Registered: 2010-10-23
- Posts: 160
Re: MBC1
What do you need it for? Are you unsure how to include an MBC1 in your circuit or do you want an equivalent circuit to know the inner workings of the MBC1?
You can check out my wiki page about MBC1 with pinout and VHDL description.
cYa,
Tauwasser
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#3 2017-04-12 21:47:21
- mjm
- New member
- Registered: 2013-02-18
- Posts: 6
Re: MBC1
I'm trying to design a 256KB ROM+MBC1 cart (no external RAM, no battery) based only on 74xxx logic. Will this work?
http://imgur.com/a/cXBN2
0000-3FFF - ROM bank 0 (A14 = 0, A15 = 0)
4000-7FFF - ROM bank 1-15 from D flip-flop as bank register (A14 = 1, A15 = 0)
8000-FFFF - non mapped (A15 = 1)
~WR change -> write D0-D3 to bank register
What wonders me:
1. D flip-flop is positive-edge-trigerred. This means that the values on D0-D3 lines should remain unchanged for some time after ~WR changes from 0 to 1 (according to doc for ~20ns). Can this be taken as granted?
2. I want to limit the number of chips to the bare minimum. I assumed that ~WR changes only when game code changes the ROM memory bank number (write to 2000-3FFF) and there are no writes to other memory areas that would cause the ~WR pin change. Am I correct?
3. Should the input to the bank register be D0-D3 or rather D4-D7?
4. Can I replace 27Cxx (UV EPROM) with 28Cxx (EEPROM) or 29Cxx (FLASH)? The pinout is the same.
Useful links:
https://dhole.github.io/post/gameboy_cartridge_emu_1/ (timings)
https://fms.kombkon.org/GameBoy/Tech/MBC1-Emu.gif (old schematic of MBC1 equivalent, not tested!)
Last edited by mjm (2017-04-12 21:49:31)
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#4 2017-04-13 13:49:19
- Tauwasser
- Member
- Registered: 2010-10-23
- Posts: 160
Re: MBC1
You logic almost works. Any writes to WRAM (0xC000 area) and the forbidden mirror RAM area (0xE000 and on) will also affect your ROM bank. You will need to make sure that A14 is low at least. Ideally, you would decode at least 3 top-most bits (A15..A13) and only enable writing when they are "001". An easy work-around may be using #CS. Make sure #CS is high while #WR is low for your write enable.
As far as hold times go, you should be fine. The bus runs with ~1 MHz in DMG mode.
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