Nitro2k01: Expanded the explanation and removed some examples that in my opinion don't clarify the issue.

2023-02-28T06:00:50Z

Expanded the explanation and removed some examples that in my opinion don't clarify the issue.

PinoBatch: found 11 examples of bitfield ordering or byte ordering

2023-02-25T23:49:26Z

found 11 examples of bitfield ordering or byte ordering

New page

The SM83 CPU core is little-endian, in which less significant bytes are stored in a lower address. This is exposed in three places:
# Instructions with 16-bit operands, such as <code>ld de, d16</code> and <code>call a16</code>. This is visible in self-modifying code in SRAM, WRAM, or HRAM.
# <code>push</code> and <code>pop</code> instructions
# <code>ld [a16], sp</code> ($08) instruction

The PPU has a mix of endiannesses.
* Pattern data ($8000-$97FF) is big-endian within a byte. The first bit to be sent to the LCD is the most significant bit.
* Pattern data is little-endian between bytes. The byte storing bit 0 of the color indices of the 8 pixels in each 8×1-pixel sliver is at a lower address than the byte storing bit 1.
* DMG color palette registers (BGP, OBP0, and OBP1) have the shade values for low color indices in low bits and high color indices in high bits.
* GBC color palette values written to BCPD and OCPD take bits 7-0 before bits 15-8, where green straddles bits 9-5.
* Addresses in DMA to VRAM are big-endian, with the more significant byte written to the lower address.

The APU is little-endian, with pulse and noise period bits 7-0 in a lower address than bits 10-8.

Cartridges are mostly little-endian.
* MBC1 bank number bits 4-0 are in a lower address than bits 6-5.
* MBC5 bank number bits 7-0 are in a lower address than bit 8.
* The 16-bit checksum in the ROM header at $014E is big-endian.

@@ Line 1: / Line 1: @@
-The SM83 CPU core is little-endian, in which less significant bytes are stored in a lower address. This is exposed in three places:
+Endianness is referring to the order that bytes comprising a word are stored in memory. Little-endian means that less significant bytes are stored in a lower memory address. Big-endian means that more significant bytes are stored in a lower memory address. Some people call little-endian "reverse endian" or similar, as values appear to be "backwards" when viewed in a hexadecimal memory viewer. For example, the 16-bit value <code>$1234</code> would be stored as the bytes <code>34 12</code> in little-endian.
 # Instructions with 16-bit operands, such as <code>ld de, d16</code> and <code>call a16</code>. This is visible in self-modifying code in SRAM, WRAM, or HRAM.
-# <code>push</code> and <code>pop</code> instructions
+Most parts of the Game Boy hardware are natively little-endian, as described below. However, when your code does not depend directly on the endianness of a certain hardware feature, you as the programmer are free to choose the endianness with which you store data.
 # <code>ld [a16], sp</code> ($08) instruction
 The PPU has a mix of endiannesses.
-* Pattern data ($8000-$97FF) is big-endian within a byte. The first bit to be sent to the LCD is the most significant bit.
+* Pattern data is little-endian between bytes. The byte storing bit 0 (the lower bitplane) of the color indices of the 8 pixels in each 8×1-pixel sliver is at a lower address than the byte storing bit 1 (the upper bitplane).
-* Pattern data is little-endian between bytes. The byte storing bit 0 of the color indices of the 8 pixels in each 8×1-pixel sliver is at a lower address than the byte storing bit 1.
-* DMG color palette registers (BGP, OBP0, and OBP1) have the shade values for low color indices in low bits and high color indices in high bits.
 * GBC color palette values written to BCPD and OCPD take bits 7-0 before bits 15-8, where green straddles bits 9-5.
-* Addresses in DMA to VRAM are big-endian, with the more significant byte written to the lower address.
+* Addresses in the GBC specific VRAM DMA are big-endian, with the most significant byte written to the lower address.
-The APU is little-endian, with pulse and noise period bits 7-0 in a lower address than bits 10-8.
+The APU is little-endian, with pulse and wave period bits 7-0 in a lower address than bits 10-8.
-Cartridges are mostly little-endian.
+Additionally, the 16-bit global checksum in the ROM header at $014E-014F is big-endian.
-* MBC1 bank number bits 4-0 are in a lower address than bits 6-5.
-* MBC5 bank number bits 7-0 are in a lower address than bit 8.
-* The 16-bit checksum in the ROM header at $014E is big-endian.

Endianness - Revision history

Nitro2k01: Expanded the explanation and removed some examples that in my opinion don't clarify the issue.

PinoBatch: found 11 examples of bitfield ordering or byte ordering