Sound Controller - Revision history

Nitro2k01 at 02:13, 5 April 2020

2020-04-05T02:13:20Z

ISSOtm: /* FF30-FF3F - Wave Pattern RAM */ Add notice about byte

2019-08-26T23:40:31Z

‎FF30-FF3F - Wave Pattern RAM: Add notice about byte

ISSOtm: /* Pitfalls */ Make pitfalls section into a list, add note about CH3 being inverted on GBA

2019-06-01T15:27:30Z

‎Pitfalls: Make pitfalls section into a list, add note about CH3 being inverted on GBA

ISSOtm: /* Pitfalls */ Add discovery on CH3 being inverted. To quote Liji: This is idiotic / It's intentional, but why would they do it

2019-06-01T15:13:18Z

‎Pitfalls: Add discovery on CH3 being inverted. To quote Liji: This is idiotic / It's intentional, but why would they do it

ISSOtm: /* APU technical explanation */ Fix mistakes

2019-05-31T20:16:10Z

‎APU technical explanation: Fix mistakes

ISSOtm: /* Pitfalls */ Reword and fix CH3 latching explanation (credits go to PinoBatch), add note about output level

2019-05-31T20:15:38Z

‎Pitfalls: Reword and fix CH3 latching explanation (credits go to PinoBatch), add note about output level

ISSOtm: /* Pitfalls */ Add another condition under which a pop my be heard

2019-05-31T20:10:38Z

‎Pitfalls: Add another condition under which a pop my be heard

ISSOtm: Add sections about technical explanations

2019-05-31T19:59:53Z

Add sections about technical explanations

PinoBatch: /* FF24 - NR50 - Channel control / ON-OFF / Volume (R/W) */ No licensed games use this, not even Pocket Music, and it's not on GBA

2019-04-18T02:15:39Z

‎FF24 - NR50 - Channel control / ON-OFF / Volume (R/W): No licensed games use this, not even Pocket Music, and it's not on GBA

PinoBatch: /* Sound Control Registers */ Clarify based on my tests: SO2 = left

2018-07-29T01:48:12Z

‎Sound Control Registers: Clarify based on my tests: SO2 = left

← Older revision		Revision as of 02:13, 5 April 2020
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−	{{Pandocs\|~~soundcontroller~~}}	+	{{Pandocs\|sound-controller}}

	== Sound Overview ==		== Sound Overview ==

@@ Line 167: / Line 167: @@
 ===FF30-FF3F - Wave Pattern RAM===
-Contents - Waveform storage for arbitrary sound data
+  Contents - Waveform storage for arbitrary sound data
-This storage area holds 32 4-bit samples that are played back upper 4 bits first.
+This storage area holds 32 4-bit samples that are played back, upper 4 bits first.
 == Sound Channel 4 - Noise ==

@@ Line 251: / Line 251: @@
 ==Pitfalls==
-Enabling or disabling a DAC (resetting NR30 bit 7 or writing %0000 0XXX to NRx2 for other channels), adding or removing it using NR51, or changing the volume in NR50, will cause an audio pop. (This causes a change in DC offset, which is smoothed out by a high-pass circuit over time, but still creates a pop)
+* Enabling or disabling a DAC (resetting NR30 bit 7 or writing %0000 0XXX to NRx2 for other channels), adding or removing it using NR51, or changing the volume in NR50, will cause an audio pop. (This causes a change in DC offset, which is smoothed out by a high-pass circuit over time, but still creates a pop)
-When first starting up a pulse channel, it will ''always'' output a (digital) zero.
+* The final output goes through a high-pass filter, which is more aggressive on GBA than on GBC, which is more aggressive than on DMG. (What this means is that the output is "pulled" towards 0V with various degrees of "aggressiveness")
-The pulse channels' "duty step" (at which position in the duty cycle they are) can't be reset. The exception to this is turning off the APU, which causes them to start over from 0 when turning it on.
+* When first starting up a pulse channel, it will ''always'' output a (digital) zero.
-Restarting a pulse channel causes its "duty step timer" to reset, meaning that "tickling" a pulse channel regularly enough will cause its "duty step" to never advance.
+* The pulse channels' "duty step" (at which position in the duty cycle they are) can't be reset. The exception to this is turning off the APU, which causes them to start over from 0 when turning it on.
-When restarting CH3, it resumes playing the last 4-bit sample it read from wave RAM, or 0 if no sample has been read since APU reset. (Sample latching is independent of output level control in NR32.) After the latched sample completes, it starts with the second sample in wave RAM (low 4 bits of $FF30). The first sample (high 4 bits of $FF30) is played last.
+* Restarting a pulse channel causes its "duty step timer" to reset, meaning that "tickling" a pulse channel regularly enough will cause its "duty step" to never advance.
-CH3 output level control does not, in fact, alter the output level. It shifts the '''digital''' value CH3 is outputting (read below), not the analog value.
+* When restarting CH3, it resumes playing the last 4-bit sample it read from wave RAM, or 0 if no sample has been read since APU reset. (Sample latching is independent of output level control in NR32.) After the latched sample completes, it starts with the second sample in wave RAM (low 4 bits of $FF30). The first sample (high 4 bits of $FF30) is played last.
-On GBA, CH3 is inverted. This causes the channel to output a loud spike when disabled; it's a good idea to "remove" the channel using NR51 while refreshing wave RAM.
+* CH3 output level control does not, in fact, alter the output level. It shifts the '''digital''' value CH3 is outputting (read below), not the analog value.
 ==APU technical explanation==

← Older revision		Revision as of 15:13, 1 June 2019
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	CH3 output level control does not, in fact, alter the output level. It shifts the '''digital''' value CH3 is outputting (read below), not the analog value.		CH3 output level control does not, in fact, alter the output level. It shifts the '''digital''' value CH3 is outputting (read below), not the analog value.
		+
		+	On GBA, CH3 is inverted. This causes the channel to output a loud spike when disabled; it's a good idea to "remove" the channel using NR51 while refreshing wave RAM.

	==APU technical explanation==		==APU technical explanation==

@@ Line 265: / Line 265: @@
 ==APU technical explanation==
 ===Game Boy, Game Boy Color===
-Each of the 4 channels work pretty identically. First, there's a "generation" circuit, which usually outputs either a 0 or another value (CH3 differs in that it can output multiple values, but regardless). That value is digital, and can range between 0 and 7. This is then fed to a [https://en.wikipedia.org/wiki/Digital-to-analog_converter DAC], which maps this to an analog value; 7 maps to the lowest (negative) voltage, 0 to the highest (positive) one. Finally, all channels are mixed through NR51, scaled through NR50, and sent to the output.
+Each of the 4 channels work pretty identically. First, there's a "generation" circuit, which usually outputs either a 0 or another value (CH3 differs in that it can output multiple values, but regardless). That value is digital, and can range between 0 and 0xF. This is then fed to a [https://en.wikipedia.org/wiki/Digital-to-analog_converter DAC], which maps this to an analog value; 7 maps to the lowest (negative) voltage, 0 to the highest (positive) one. Finally, all channels are mixed through NR51, scaled through NR50, and sent to the output.
-Each DAC is controlled independently from the generation circuit. For CH3, the DAC is controlled by NR30 bit 7; for other channels, the DAC is turned on unless bits 3-7 of NRx2 are reset, and the values output will be 0 and <code>[NRx2] >> 4</code>. The generation circuits are turned on by restarting them for the first time, and this is what sets the corresponding bit in NR52. Yes, it's possible to turn on a DAC but not the generation circuit. Finally, disabling a DAC also kills the generation circuit.
+Each DAC is controlled independently from the generation circuit. For CH3, the DAC is controlled by NR30 bit 7; for other channels, the DAC is turned on unless bits 3-7 of NRx2 are reset, and the envelope will be set to <code>[NRx2] >> 4</code>. (Note: the envelope sweep function changes the envelope, but not the value in NRx2! It won't disable the DAC, either.) The generation circuits are turned on by restarting them for the first time, and this is what sets the corresponding bit in NR52. Yes, it's possible to turn on a DAC but not the generation circuit. Finally, disabling a DAC also kills the generation circuit.
-Note that each DAC has a DC offset, so enabling, disabling, adding to or removing from NR51, will all cause an audio pop.
+Note that each DAC has a DC offset, so enabling, disabling, adding to or removing from NR51, will all cause an audio pop; changing the volume in NR50 will as well.
 Finally, all the output goes through a high-pass filter to remove the DC offsets from the DACs.
@@ Line 277: / Line 277: @@
 This means that the APU has no DACs, or if modelling the GBA as a GB, they're always on.
 == Read more ==

← Older revision		Revision as of 19:59, 31 May 2019
Line 249:		Line 249:

	Bits 0-3 of this register are read only status bits, writing to these bits does NOT enable/disable sound. The flags get set when sound output is restarted by setting the Initial flag (Bit 7 in NR14-NR44), the flag remains set until the sound length has expired (if enabled). A volume envelopes which has decreased to zero volume will NOT cause the sound flag to go off.		Bits 0-3 of this register are read only status bits, writing to these bits does NOT enable/disable sound. The flags get set when sound output is restarted by setting the Initial flag (Bit 7 in NR14-NR44), the flag remains set until the sound length has expired (if enabled). A volume envelopes which has decreased to zero volume will NOT cause the sound flag to go off.
		+
		+	==Pitfalls==
		+	Enabling or disabling a DAC (resetting NR30 bit 7 or writing %0000 0XXX to NRx2 for other channels), adding or removing it using NR51, will cause an audio pop. (This causes a change in DC offset, which is smoothed out by a high-pass circuit over time, but still creates a pop)
		+
		+	When first starting up a pulse channel, it will ''always'' output a (digital) zero.
		+
		+	The pulse channels' "duty step" (at which position in the duty cycle they are) can't be reset. The exception to this is turning off the APU, which causes them to start over from 0 when turning it on.
		+
		+	Restarting a pulse channel causes its "duty step timer" to reset, meaning that "tickling" a pulse channel regularly enough will cause its "duty step" to never advance.
		+
		+	When turning off CH3, the nibble being played is latched, but may become a 0 over time (TODO: this needs to be researched. Do individual bits decay?). When turning the channel on again, that value is played first, then the second nibble (lower 4 bits of $FF30) plays.
		+
		+
		+	==APU technical explanation==
		+	===Game Boy, Game Boy Color===
		+	Each of the 4 channels work pretty identically. First, there's a "generation" circuit, which usually outputs either a 0 or another value (CH3 differs in that it can output multiple values, but regardless). That value is digital, and can range between 0 and 7. This is then fed to a [https://en.wikipedia.org/wiki/Digital-to-analog_converter DAC], which maps this to an analog value; 7 maps to the lowest (negative) voltage, 0 to the highest (positive) one. Finally, all channels are mixed through NR51, scaled through NR50, and sent to the output.
		+
		+	Each DAC is controlled independently from the generation circuit. For CH3, the DAC is controlled by NR30 bit 7; for other channels, the DAC is turned on unless bits 3-7 of NRx2 are reset, and the values output will be 0 and <code>[NRx2] >> 4</code>. The generation circuits are turned on by restarting them for the first time, and this is what sets the corresponding bit in NR52. Yes, it's possible to turn on a DAC but not the generation circuit. Finally, disabling a DAC also kills the generation circuit.
		+
		+	Note that each DAC has a DC offset, so enabling, disabling, adding to or removing from NR51, will all cause an audio pop.
		+
		+	Finally, all the output goes through a high-pass filter to remove the DC offsets from the DACs.
		+
		+	===Game Boy Advance===
		+	The APU was reworked pretty heavily for the GBA. Instead of mixing being done analogically, it's instead done digitally; then, sound is converted to an analog signal and an offset is added (see SOUNDBIAS in [http://problemkaputt.de/gbatek.htm#gbasoundcontrolregisters GBATEK] for more details.
		+
		+	This means that the APU has no DACs, or if modelling the GBA as a GB, they're always on.
		+

	== Read more ==		== Read more ==

@@ Line 222: / Line 222: @@
    Bit 2-0 - SO1 output level (volume)  (0-7)
-The Vin signal is received from the game cartridge bus, allowing external hardware in the cartridge to supply a fifth sound channel, additionally to the gameboys internal four channels. As far as I know this feature isn't used by any existing games.
+The Vin signal is an analog signal received from the game cartridge bus, allowing external hardware in the cartridge to supply a fifth sound channel, additionally to the Game Boy's internal four channels. No licensed games used this feature, and it was omitted from the Game Boy Advance.
 ===FF25 - NR51 - Selection of Sound output terminal (R/W)===

@@ Line 215: / Line 215: @@
 ===FF24 - NR50 - Channel control / ON-OFF / Volume (R/W)===
-The volume bits specify the "Master Volume" for Left/Right sound output.
+The volume bits specify the "Master Volume" for Left/Right sound output. SO2 goes to the left headphone, and SO1 goes to the right.
    Bit 7   - Output Vin to SO2 terminal (1=Enable)
@@ Line 225: / Line 225: @@
 ===FF25 - NR51 - Selection of Sound output terminal (R/W)===
    Bit 7 - Output sound 4 to SO2 terminal
@@ Line 246: / Line 247: @@
 Bits 0-3 of this register are read only status bits, writing to these bits does NOT enable/disable sound. The flags get set when sound output is restarted by setting the Initial flag (Bit 7 in NR14-NR44), the flag remains set until the sound length has expired (if enabled). A volume envelopes which has decreased to zero volume will NOT cause the sound flag to go off.
 == Read more ==