Timer Obscure Behaviour - Revision history

AntonioND at 10:50, 23 November 2014

2014-11-23T10:50:51Z

2014-11-23T00:16:23Z

2014-11-23T00:15:28Z

2014-11-22T23:58:05Z

‎Relation between Timer and Divider register

2014-11-22T23:43:25Z

Created page with '===Relation between Timer and Divider register=== TODO...'

New page

===Relation between Timer and Divider register===

TODO...

@@ Line 41: / Line 41: @@
 ==Timer Overflow Behaviour==
-When TIMA overflows, the value from TMA is loaded and IF timer flag is set to 1, but this doesn't happen immediately. Timer interrupt is delayed 1 cycle (4 clocks) from the TIMA overflow. The TMA reload to TIMA is also delayed. For one cycle, after overflowing TIMA, the value in TIMA is 00h, not TMA.
+When TIMA overflows, the value from TMA is loaded and IF timer flag is set to 1, but this doesn't happen immediately. Timer interrupt is delayed 1 cycle (4 clocks) from the TIMA overflow. The TMA reload to TIMA is also delayed. For one cycle, after overflowing TIMA, the value in TIMA is 00h, not TMA. This happens only when an overflow happens, not when the upper bit goes from 1 to 0, it can't be done manually writing to TIMA, the timer has to increment itself.
 For example (SYS is the system internal counter divided by 4 for easier understanding, each increment of the graph is 1 cycle, not 1 clock):

@@ Line 3: / Line 3: @@
 [[File:Timer_simplified.png]]
-===Relation between Timer and Divider register===
+==Relation between Timer and Divider register==
 This is a schematic of the circuit involving TAC and DIV:
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 The sentence marked with a (*) has a different behaviour in GBC (AGB and AGS seem to have strange behaviour even in the other statements). When enabling the timer and maintaining the same frequency it doesn't glitch. When disabling the timer it doesn't glitch either. When another change of value happens (so timer is enabled after the write), the behaviour depends on a race condition, so it cannot be predicted for every device.
-===Timer Overflow Behaviour===
+==Timer Overflow Behaviour==
 When TIMA overflows, the value from TMA is loaded and IF timer flag is set to 1, but this doesn't happen immediately. Timer interrupt is delayed 1 cycle (4 clocks) from the TIMA overflow. The TMA reload to TIMA is also delayed. For one cycle, after overflowing TIMA, the value in TIMA is 00h, not TMA.

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 ===Relation between Timer and Divider register===
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 END IF
 </pre>

← Older revision		Revision as of 23:58, 22 November 2014
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	===Relation between Timer and Divider register===		===Relation between Timer and Divider register===

−	~~TODO~~...	+	This is a schematic of the circuit involving TAC and DIV:
		+
		+	[[File:Timer_tac_bug_dmg.png]]
		+
		+	Notice how the values that are connected to the inputs of the multiplexer are the values of those bits, not the carry of those bits. This is the reason of a few things:
		+
		+	- When writing to DIV, the whole counter is reseted, so the timer is also affected.
		+
		+	- When writing to DIV, if the current output is '1' and timer is enabled, as the new value after reseting DIV will be '0', the falling edge detector will detect a falling edge and TIMA will increase.
		+
		+	- When writing to TAC, if the previously selected multiplexer input was '1' and the new input is '0', TIMA will increase too. This doesn't happen when the timer is disabled, but it also happens when disabling the timer (the same effect as writing to DIV). The following code explains the behaviour in DMG and MGB.
		+
		+	<pre>
		+	clocks_array[4] = {1024, 16, 64, 256}
		+
		+	old_clocks = clocks_array[old_TAC&3]
		+	new_clocks = clocks_array[new_TAC&3]
		+
		+	old_enable = old_TAC & BIT(2)
		+	new_enable = new_TAC & BIT(2)
		+
		+	sys_clocks = 16 bit system counter
		+
		+	IF old_enable == 0 THEN
		+	glitch = 0 (*)
		+	ELSE
		+	IF new_enable == 0 THEN
		+	glitch = (sys_clocks & (old_clocks/2)) != 0
		+	ELSE
		+	glitch = ((sys_clocks & (old_clocks/2)) != 0) && ((sys_clocks & (new_clocks/2)) == 0)
		+	END IF
		+	END IF
		+	</pre>