Timer and Divider Registers - Revision history

Nitro2k01 at 02:15, 5 April 2020

2020-04-05T02:15:29Z

AntonioND at 23:44, 22 November 2014

2014-11-22T23:44:47Z

AntonioND at 23:43, 22 November 2014

2014-11-22T23:43:05Z

Beannaich: /* FF04 - DIV - Divider Register (R/W) */

2012-05-25T12:07:44Z

‎FF04 - DIV - Divider Register (R/W)

Beannaich: /* FF07 - TAC - Timer Control (R/W) */

2012-05-25T12:02:18Z

‎FF07 - TAC - Timer Control (R/W)

Beannaich: /* FF07 - TAC - Timer Control (R/W) */

2012-05-25T11:54:14Z

‎FF07 - TAC - Timer Control (R/W)

Xzakox at 12:50, 28 June 2009

2009-06-28T12:50:54Z

Xzakox: /* INT 50 - Timer Interrupt */

2009-06-28T10:39:42Z

‎INT 50 - Timer Interrupt

Xzakox: New page: ===FF04 - DIV - Divider Register (R/W)=== This register is incremented at rate of 16384Hz (~16779Hz on SGB). In CGB Double Speed Mode it is incremented twice as fast, ie. at 32768Hz. Writi...

2009-06-28T10:38:31Z

New page: ===FF04 - DIV - Divider Register (R/W)=== This register is incremented at rate of 16384Hz (~16779Hz on SGB). In CGB Double Speed Mode it is incremented twice as fast, ie. at 32768Hz. Writi...

New page

===FF04 - DIV - Divider Register (R/W)===
This register is incremented at rate of 16384Hz (~16779Hz on SGB). In CGB Double Speed Mode it is incremented twice as fast, ie. at 32768Hz. Writing any value to this register resets it to 00h.

===FF05 - TIMA - Timer counter (R/W)===
This timer is incremented by a clock frequency specified by the TAC register ($FF07). When the value overflows (gets bigger than FFh) then it will be reset to the value specified in TMA (FF06), and an interrupt will be requested, as described below.

===FF06 - TMA - Timer Modulo (R/W)===
When the TIMA overflows, this data will be loaded.

===FF07 - TAC - Timer Control (R/W)===

Bit 2 - Timer Stop (0=Stop, 1=Start)
Bits 1-0 - Input Clock Select
00: 4096 Hz (~4194 Hz SGB)
01: 262144 Hz (~268400 Hz SGB)
10: 65536 Hz (~67110 Hz SGB)
11: 16384 Hz (~16780 Hz SGB)

===INT 50 - Timer Interrupt===
Each time when the timer overflows (ie. when TIMA gets bigger than FFh), then an interrupt is requested by setting Bit 2 in the IF Register (FF0F). When that interrupt is enabled, then the CPU will execute it by calling the timer interrupt vector at 0050h.

'''Note'''
The above described Timer is the built-in timer in the gameboy. It has nothing to do with the MBC3s battery buffered Real Time Clock - that's a completely different thing, described in the chapter about Memory Banking Controllers.

← Older revision		Revision as of 02:15, 5 April 2020
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−	{{Pandocs\|~~timeranddividerregisters~~}}	+	{{Pandocs\|timer-and-divider-registers}}

	===FF04 - DIV - Divider Register (R/W)===		===FF04 - DIV - Divider Register (R/W)===

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 {{Pandocs|timeranddividerregisters}}
 ===FF04 - DIV - Divider Register (R/W)===
 This register is incremented at rate of 16384Hz (~16779Hz on SGB). Writing any value to this register resets it to 00h.

← Older revision		Revision as of 12:50, 28 June 2009
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		+	{{Pandocs\|timeranddividerregisters}}
	===FF04 - DIV - Divider Register (R/W)===		===FF04 - DIV - Divider Register (R/W)===
	This register is incremented at rate of 16384Hz (~16779Hz on SGB). In CGB Double Speed Mode it is incremented twice as fast, ie. at 32768Hz. Writing any value to this register resets it to 00h.		This register is incremented at rate of 16384Hz (~16779Hz on SGB). In CGB Double Speed Mode it is incremented twice as fast, ie. at 32768Hz. Writing any value to this register resets it to 00h.

@@ Line 1: / Line 1: @@
 {{Pandocs|timeranddividerregisters}}
 ===FF04 - DIV - Divider Register (R/W)===
@@ Line 27: / Line 25: @@
 ===INT 50 - Timer Interrupt===
 Each time when the timer overflows (ie. when TIMA gets bigger than FFh), then an interrupt is requested by setting Bit 2 in the IF Register (FF0F). When that interrupt is enabled, then the CPU will execute it by calling the timer interrupt vector at 0050h.
 == Note ==
 The above described Timer is the built-in timer in the gameboy. It has nothing to do with the MBC3s battery buffered Real Time Clock - that's a completely different thing, described in the chapter about Memory Banking Controllers.

@@ Line 11: / Line 11: @@
 ===FF07 - TAC - Timer Control (R/W)===
-   Bit 2    - Timer Stop  (0=Stop, 1=Start)
+   Bit  2   - Timer Enable
    Bits 1-0 - Input Clock Select
-:   4096 Hz    (~4194 Hz SGB)
+: CPU Clock / 1024 (DMG, CGB:   4096 Hz, SGB:   ~4194 Hz)
-: 262144 Hz  (~268400 Hz SGB)
+: CPU Clock / 16   (DMG, CGB: 262144 Hz, SGB: ~268400 Hz)
-:  65536 Hz   (~67110 Hz SGB)
+: CPU Clock / 64   (DMG, CGB:  65536 Hz, SGB:  ~67110 Hz)
-:  16384 Hz   (~16780 Hz SGB)
+: CPU Clock / 256  (DMG, CGB:  16384 Hz, SGB:  ~16780 Hz)
-   Note: The FF07.2 only affects the timer. The divider is *ALWAYS* counting, regardless of if the timer is or isn't.
+   Note: The "Timer Enable" bit only affects the timer, the divider is '''ALWAYS''' counting.
 ===INT 50 - Timer Interrupt===