# Difference between revisions of "ADC"

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+ | {{Opcode}} | ||

== Add With Carry == | == Add With Carry == | ||

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The ''half-carry'' flag bit is set to 1 if the operation causes a mathematical carry from bit 3. | The ''half-carry'' flag bit is set to 1 if the operation causes a mathematical carry from bit 3. | ||

+ | The ''half-carry'' flag can be tricky sometimes to set properly. For this operation it can be recommended that you use some form of the equation below. | ||

+ | |||

+ | ''half-carry'' = ((lower nibble of CPU register A) + (lower nibble of the input register) + (carry flag (if set, put 0x1)) > 0xF) ? (boolean true) : (boolean false) | ||

+ | |||

+ | An alternative to this is: | ||

+ | |||

+ | ''half-carry'' = ((A & operand) | ((A ^ operand) & ~(A + operand + carry))) & $08 | ||

+ | |||

+ | where 'operand' is the register, or immediate byte specified by the instruction. | ||

---- | ---- | ||

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OP Code #CE | OP Code #CE | ||

− | ''n'' is the value of the byte of memory stored at a certain location, where the 16-bit address is the program counter | + | ''n'' is the value of the byte of memory stored at a certain location, where the 16-bit address of the memory is the program counter. You must increment the program counter after the operation and wrap to a 16-bit length as appropriate. |

## Latest revision as of 12:09, 25 May 2012

**This is an article about the GB-Z80 CPU.**

Opcodes:

**Arithmetic and logical:** ADD - ADD (16-bit) including LD HL,SP+nn - **ADC** - AND - CP - CPL - DAA - DEC - DEC and INC (16-bit) - INC - SBC - SUB - OR - XOR

**Conditional:** CALL - JP - JR - RET

**Load:** LD (8-bit) - LD (16-bit)

**Extended Set:** BIT - RES - RL - RLC - RR - RRC - SET - SLA - SRA - SRL - SWAP

## Add With Carry

This opcode group adds the contents of the specified byte-valued input and the register F *carry* flag (Flag computed as a 1 or a 0) to the contents of register A, to be stored in register A.
The formula can be seen as A=A+r+CY. Since register A is an 8-bit register, you must make sure it wraps around appropriately to only contain an 8-bit value in the range of 0-0xFF (0-255).

The ADC operation code groups are known as follows:

1) *ADC A, r*

2) *ADC A, n*

3) *ADC A, (HL)*

**Register F Flag Computation**

The *subtract* flag bit is *always* reset to 0 for any ADC operation.
The *zero* flag bit is set to 1 if the operation sets register A to 0, otherwise the *zero* flag is reset to 0.
The *carry* flag bit is set to 1 if the operation causes a mathematical carry from bit 7.
The *half-carry* flag bit is set to 1 if the operation causes a mathematical carry from bit 3.

The *half-carry* flag can be tricky sometimes to set properly. For this operation it can be recommended that you use some form of the equation below.

*half-carry* = ((lower nibble of CPU register A) + (lower nibble of the input register) + (carry flag (if set, put 0x1)) > 0xF) ? (boolean true) : (boolean false)

An alternative to this is:

*half-carry* = ((A & operand) | ((A ^ operand) & ~(A + operand + carry))) & $08

where 'operand' is the register, or immediate byte specified by the instruction.

**ADC A, r**

Machine Cycle Count: 1

*r* is a CPU register as specified in the table below.

# | Register (in place of r) |

8F | A |

88 | B |

89 | C |

8A | D |

8B | E |

8C | H |

8D | L |

**ADC A, n**

Machine Cycle Count: 2

OP Code #CE

*n* is the value of the byte of memory stored at a certain location, where the 16-bit address of the memory is the program counter. You must increment the program counter after the operation and wrap to a 16-bit length as appropriate.

**ADC A, (HL)**

Machine Cycle Count: 2

OP Code #8E

*(HL)* is the value of the byte of memory stored at a certain location, where the address is the 16-bit value of registers H and L, being that register H is the upper byte, and register L is the lower byte.