Difference between revisions of "BIT"

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(Created page with '{{Opcode}} This instruction is part of the $CB prefixed extended instruction set.<br> This instruction group tests various bits of the various registers, or memory location. It …')
 
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{{Opcode}}
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{{Instruction|
 
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  Name=BIT |
This instruction is part of the $CB prefixed extended instruction set.<br>
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  Description=This instruction group tests various bits of the various registers, or memory location. |
This instruction group tests various bits of the various registers, or memory location. It is encoded as follows:
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  Encoding=01bbbrrr
 
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  01bbbrrr
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r: Register
  | || |
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b: Bit to test
  | |+-+- Register
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  +-+---- Bit to test ('b' has a binary weight of 2^b)
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  Where register is one of the following:
 
  Where register is one of the following:
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  101: L    - 2 Machine Cycles
 
  101: L    - 2 Machine Cycles
 
  110: (HL) - 3 Machine Cycles
 
  110: (HL) - 3 Machine Cycles
  111: A    - 2 Machine Cycles
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  111: A    - 2 Machine Cycles |
 
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  Z=1 if specified bit is 0; 0 otherwise |
== Flags ==
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  H=1 |
 
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  N=0}}
Z: 1 if specified bit is 0; 0 otherwise
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H: 1
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N: 0
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C: -
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Revision as of 13:01, 25 May 2012

This is an article about the GB-Z80 CPU.

Opcodes:

Arithmetic and logical: ADD - ADD (16-bit) including LD HL,SP+nn - ADC - AND - CP - CPL - DAA - DEC - DEC and INC (16-bit) - INC - SBC - SUB - OR - XOR
Conditional: CALL - JP - JR - RET
Load: LD (8-bit) - LD (16-bit)
Extended Set: BIT - RES - RL - RLC - RR - RRC - SET - SLA - SRA - SRL - SWAP

This instruction group tests various bits of the various registers, or memory location.

Encoding

01bbbrrr

r: Register
b: Bit to test

Where register is one of the following:

000: B    - 2 Machine Cycles
001: C    - 2 Machine Cycles
010: D    - 2 Machine Cycles
011: E    - 2 Machine Cycles
100: H    - 2 Machine Cycles
101: L    - 2 Machine Cycles
110: (HL) - 3 Machine Cycles
111: A    - 2 Machine Cycles

Flags

Z: 1 if specified bit is 0; 0 otherwise
N: 0
H: 1