Gameboy Development Forum

Tag365 · 2024-07-26 12:14:53

How hard would it be to develop a Game Boy memory bank controller that supports switching to 256*256 banks worth (1 GB) of ROM data and 256 banks worth (2 MB) of cartridge RAM? The most memory I know that existing MBCs can access is 512 banks worth (8 MB) of ROM data and 16 banks worth (128 KB) of RAM. Is extending the RAM as simple as adding more memory and more available banks to switch? How would ROM bank switching work? You can't change just one byte to access the whole 65,536 banks of ROM, so a system would have to be in place to switch ROM banks only after the two bytes used for selecting the ROM bank have been changed, or it would require you to use 16 bit values for ROM bank selection.

Yeah, 1 GB ROM and 2 MB RAM would be way more than what an average homebrew application or game for Game Boy would need (except RAM for a block building game, which needs lots of space to save terrain and world data), but I wanted to see what people think of the difficulties of implementing such a memory bank controller are and the obstacles that are believed to occur when making such a unit. I don't plan on making one myself either, this is just a discussion thread.

nitro2k01 · 2024-07-26 15:22:17

In principle. it should be fairly doable.

First you need a specification of how to interface with a mapper like that. One such specification is TPP1. It's supported in some emulators, but has as far as I'm aware never been implemented in hardware. I personally have a gripe with this specification because it doesn't even try to be backward compatible with regular MBCs in cases where it could be. MBC5 officially supports up to 512 banks, by using allowing you to write to the 3000-3fff range to set a ninth address bit. A reasonable way of extending this would be to consider (up to) all 8 bits of writes to this register, for up to 65536 ROM banks.

Then you need an implementation. This would be easy in an emulator, where you can pretty much just do whatever you want. As for hardware, you could easily add the extra addressing in a FPGA implementation of a MBC. There are other issues in implementing it in hardware. If you want to use DRAM in place of either flash or SRAM, you need to take into account the DRAM refresh time. The Gameboy needs the data back in less than 1 much less than 1 microsecond whereas DRAM refresh can take multiple microseconds. The cartridge has no way of signalling back to the Gameboy that it should wait, so you need some way around this issue if you go that route.

Tag365 · 2024-07-26 23:47:44

nitro2k01 wrote:
In principle. it should be fairly doable.

First you need a specification of how to interface with a mapper like that. One such specification is TPP1. It's supported in some emulators, but has as far as I'm aware never been implemented in hardware. I personally have a gripe with this specification because it doesn't even try to be backward compatible with regular MBCs in cases where it could be. MBC5 officially supports up to 512 banks, by using allowing you to write to the 3000-3fff range to set a ninth address bit. A reasonable way of extending this would be to consider (up to) all 8 bits of writes to this register, for up to 65536 ROM banks.

The extension of the ninth ROM address bit into a second address byte and the RAM address half-byte into a full 8 bits was an obvious idea, to the point of having me thinking why didn't they do that in the first place for the original MBC5. I guess it was due to monetary reasons to reduce the price by removing complexity in the physical design of such cartridges.

As for the specification, what kind of specification do you think would work the best for the 65,536 ROM banks? Is extending the MBC5 like specification to 65,536 ROM banks and 256 RAM banks enough for this? Or is your ideal specification a divergence from this, and in what ways if true? Does TPP1 have any good ideas, and if so would they fit well for your ideal specification?

nitro2k01 · 2024-07-27 13:14:27

The idea of TPP1 is great. My aforementioned gripe with TPP1 is with the choice of addresses for its control registers, as well as some of the aspects of the header information. Basically, I would've loved if TPP1 was equivalent to MBC5 for any ROM that didn't use RTC, or extended memory, so that a hypothetical TPP1 flashcart would be mostly backward compatible if you wanted to run regular ROMs on it.

As for MBC5, I guess the limiting factor was, as you said, money. But more specifically the number of pins on the MBC chip. More address bits would need more pin, and the MBC chip would have to be bumped up from QFP32 (32 pin quad flat package) to the next standard size of QFP44, adding 12 more pins. This would cost more to manufacture, and take up more board area, so they probably decided against it. Other than the physical changes, just adding more address bits would be a trivial change to the design.

Gameboy Development Forum

#1 2024-07-26 12:14:53

Difficulty of developing an MBC supporting 1 GB of ROM + 2 MB of SRAM

#2 2024-07-26 15:22:17

Re: Difficulty of developing an MBC supporting 1 GB of ROM + 2 MB of SRAM

#3 2024-07-26 23:47:44

Re: Difficulty of developing an MBC supporting 1 GB of ROM + 2 MB of SRAM

nitro2k01 wrote:

#4 2024-07-27 13:14:27

Re: Difficulty of developing an MBC supporting 1 GB of ROM + 2 MB of SRAM

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