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Discussion about software development for the old-school Gameboys, ranging from the "Gray brick" to Gameboy Color
(Launched in 2008)

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#1 2020-04-16 13:40:25

Ben
Member
Registered: 2015-01-21
Posts: 10

Hardware address restriction

Hi,

I'm currently developing a custom cartridge and I wanted the confirmation that it is possible to try writing data in the ROM reserved addresses (0x0000 - 0x7000). I assume that it is possible, because the MBC management use this, but I'd like someone to confirm my assumption.

Also, I've been looking to this schematic of the internal circuitry of the GB: https://fms.komkon.org/GameBoy/Tech/GameBoy.gif
I'm a bit confuse by the internal RAM (U3) control lines connection. With the described connection, the internal RAM is enable each time CS\ is low and A13 is high. Therefore there would be conflict between the internal and the external RAM each time we try to read the eternal RAM (0xA000 - 0xBFFF) where A13 is high. And the internal RAM wouldn't be enabled when we would use the internal RAM address (0xC000 - 0xD000) where A13 is low. Does anyone have more information on this subject ?

Thanks


[Ben]
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#2 2020-04-16 17:25:43

Tauwasser
Member
Registered: 2010-10-23
Posts: 160

Re: Hardware address restriction

Ben wrote:

I'm currently developing a custom cartridge and I wanted the confirmation that it is possible to try writing data in the ROM reserved addresses (0x0000 - 0x7000). I assume that it is possible, because the MBC management use this, but I'd like someone to confirm my assumption.

Yes, that's exactly how it works and how the MBCs are written to.

Ben wrote:

Also, I've been looking to this schematic of the internal circuitry of the GB: https://fms.komkon.org/GameBoy/Tech/GameBoy.gif
I'm a bit confuse by the internal RAM (U3) control lines connection. With the described connection, the internal RAM is enable each time CS\ is low and A13 is high. Therefore there would be conflict between the internal and the external RAM each time we try to read the eternal RAM (0xA000 - 0xBFFF) where A13 is high. And the internal RAM wouldn't be enabled when we would use the internal RAM address (0xC000 - 0xD000) where A13 is low. Does anyone have more information on this subject ?

Yeah, that's a long-standing issue. The positive CS pin is connected to A14 (I just checked my DMG to make sure), so WRAM is active in 0xC000--0xDFFF region (as one would expect) and also in 0xE000--0xFDFF region (mirror WRAM). The region 0xFE00--0xFFFF does not assert #CS, so it is not included in the "mirror WRAM" region. See Gekkio's Game Boy: Complete Technical Reference for reference. The bus timing diagrams are in section C.1.

Best of luck with your project big_smile

Last edited by Tauwasser (2020-04-16 17:27:06)

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#3 2020-04-16 18:09:49

Ben
Member
Registered: 2015-01-21
Posts: 10

Re: Hardware address restriction

Thank you for your answer and the technical reference, it makes more sense now.
And a special thanks for the physical verification !


[Ben]
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