Discussion about software development for the old-school Gameboys, ranging from the "Gray brick" to Gameboy Color
(Launched in 2008)
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Hello,
I'm trying to understand how the read operation works on the cartridge of a DMG-01. If I understand correctly, the GB should set the RD pin and unset the WR pin after setting the address on the A0-A15 pins.
My problem is that either while testing directly on the GB port, or with a dummy breakout cartridge, or with my own cartridge with an µC on it, RD never changes, from the boot to the end of the logo, and stays to GND level.
I Tested with an oscilloscope (which perfectly sees the CLK signal and the address pins change), but the RD pin stays depressingly low all the time.
All commercial cartridges work just fine, so the GB hardware is not at fault, I guess my brain is.
Is there something to do for the GB to toggle the RD pin ?
Thanks a lot for any help !
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Hi. Your understanding is wrong. There's no requirement for the /RD signal to produce any edges. Instead think of it as requesting data from whatever address is on the address bus for as long as the signal is active. The /RD signal is active low, so if it's at 0V it actually means the CPU is requesting to read data. The address may change continuously at this point.
However, one more thing comes into play. The A15 address line isn't really an address line per se. It's more of chip select line for ROM, also active low. So when it's 5V it means the CPU isn't requesting data from ROM. This is the case for most of the boot ROM execution (except when reading the logo/header data). In this case the external bus is actually in the idle state.
Dhole has previously done the same thing as you're trying to do. They used an ARM Cortex clocked at 168 MHz. Their solution was to trigger an interrupt on each rising edge of the CLK signal, wait a while for the bus signals to become valid, then check which action and address was requested.
Linked below are their writeup, which also has example code, as well as a link to gekkio's GB-CTR document which has valuable information, in particular under appendix C, Gameboy external bus.
I would probably not recommend an underpowered or 8-bit microcontroller for a project like this. Good luck!
http://dhole.github.io/post/gameboy_cartridge_emu_1/
http://dhole.github.io/post/gameboy_cartridge_emu_2/
https://gekkio.fi/files/gb-docs/gbctr.pdf
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nitro2k01 wrote:
Hi. Your understanding is wrong. There's no requirement for the /RD signal to produce any edges. Instead think of it as requesting data from whatever address is on the address bus for as long as the signal is active. The /RD signal is active low, so if it's at 0V it actually means the CPU is requesting to read data. The address may change continuously at this point.
Ho ! I've read this very Dhole page already, I'll do this more thoroughly, I missed this part. So it's all about the timing then if I understand correctly, the CLK signal is much more important that I thought.
(That's a relief on the hardware part, that means my electronics are working. Not so much on the software part which you complicated quite a bit now , and I've got some traces to re-route also but it'll be ok)
nitro2k01 wrote:
I would probably not recommend an underpowered or 8-bit microcontroller for a project like this.
I'm using a RP2040, a dual M0+ at 133Mhz, overclockable to ~200Mhz and I'm quite into optimizing low-level stuff so I guess I've got this right, at least
Thank you very much for the brain-detangling, I really needed that.
nitro2k01 wrote:
Good luck!
No no, who needs that ?
Again, thank you !
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