|
|
| Line 1: |
Line 1: |
| − | == DMG PCB Naming Convention ==
| |
| | | | |
| − | DMG PCB codes follow the following convention:
| |
| − |
| |
| − | DMG[-?[?]]-???[?][(?)]-NN
| |
| − | | | | \-- PCB revision
| |
| − | | | \------- optional code in parentheses
| |
| − | | \-------------- mandatory three or four-letter descriptor
| |
| − | \--------------------- one or two-letter optional part
| |
| − |
| |
| − | === Descriptor Codes ===
| |
| − |
| |
| − | {| class="wikitable sortable"
| |
| − | |-
| |
| − | ! Code
| |
| − | ! scope="col" class="unsortable" |MBC/Battery
| |
| − | ! scope="col" class="unsortable" |ROM Size
| |
| − | ! scope="col" class="unsortable" |RAM Size
| |
| − | ! scope="col" class="unsortable" |ROM Package
| |
| − | |-
| |
| − | | (none)
| |
| − | | -
| |
| − | | -
| |
| − | | -
| |
| − | | QFP
| |
| − | |-
| |
| − | | A
| |
| − | | none
| |
| − | | 256kbit
| |
| − | | none
| |
| − | | -
| |
| − | |-
| |
| − | | B
| |
| − | | MBC1A/MBC1B/MBC1B1
| |
| − | | 512kbit?
| |
| − | | -?
| |
| − | | -
| |
| − | |-
| |
| − | | C
| |
| − | | -
| |
| − | | 1Mbit
| |
| − | | 64kbit
| |
| − | | Chip-on-Board
| |
| − | |-
| |
| − | | D
| |
| − | | MBC1A/MBC1B/MBC1B1 + CR1616
| |
| − | | 2Mbit?
| |
| − | | 256kbit
| |
| − | | -
| |
| − | |-
| |
| − | | E
| |
| − | | -
| |
| − | | 4Mbit
| |
| − | | 512kbit
| |
| − | | -
| |
| − | |-
| |
| − | | F
| |
| − | | -
| |
| − | | 8Mbit
| |
| − | | -
| |
| − | | -
| |
| − | |-
| |
| − | | G
| |
| − | | MBC2A + CR1616
| |
| − | | 16Mbit
| |
| − | | -
| |
| − | | -
| |
| − | |-
| |
| − | | H
| |
| − | | -
| |
| − | | 32Mbit
| |
| − | | -
| |
| − | | -
| |
| − | |-
| |
| − | | K
| |
| − | | MBC3A/MBC3B + CR2025
| |
| − | | -
| |
| − | | -
| |
| − | | -
| |
| − | |-
| |
| − | | M
| |
| − | | MBC30 + CR2025
| |
| − | | -
| |
| − | | -
| |
| − | | -
| |
| − | |-
| |
| − | | N
| |
| − | | -
| |
| − | | -
| |
| − | | -
| |
| − | | SOIC (narrow)
| |
| − | |-
| |
| − | | P
| |
| − | | MMM01
| |
| − | | -
| |
| − | | -
| |
| − | | -
| |
| − | |-
| |
| − | | S
| |
| − | | MMM01 + CR1616
| |
| − | | -
| |
| − | | -
| |
| − | | -
| |
| − | |-
| |
| − | | T
| |
| − | | HuC1A + CR1616
| |
| − | | -
| |
| − | | -
| |
| − | | TSSOP
| |
| − | |-
| |
| − | | U
| |
| − | | HuC3A + CR2025
| |
| − | | -
| |
| − | | -
| |
| − | | TSOP
| |
| − | |}
| |
| − |
| |
| − | For example, DMG-BEAN-02 is a PCB made for
| |
| − | * MBC1A/MBC1B/MBC1B1 (without battery)
| |
| − | * 256kbit of ROM
| |
| − | * no SRAM
| |
| − | * ROM chip package is a narrow SOIC
| |
| − |
| |
| − | === PCB Revisions ===
| |
| − |
| |
| − | Numbers include
| |
| − |
| |
| − | *01
| |
| − | *02
| |
| − | *03
| |
| − | *10
| |
| − |
| |
| − | Mostly minor routing differences if any. Sometimes additional components in 10. Never additional components in 0x?
| |
| − |
| |
| − | === Optional Parts ===
| |
| − |
| |
| − | DMG-MC-SFCN-01 Momotarou Collection 2
| |
| − | DMG-M-PEAN-10 Taito Variety Pack
| |
| − |
| |
| − | MC = Momotarou Collection? MultiCart?
| |
| − |
| |
| − | Code in parentheses after descriptor is only ever K.
| |
| − |
| |
| − | DMG-BEAN(K)-10 Xenon 2
| |
| − | DMG-DECN(K)-02 Mogurania (Mole Mania)
| |
| − |
| |
| − |
| |
| − | == CGB PCB Naming Convention ==
| |
| − |
| |
| − | CGB PCB codes follow the following convention:
| |
| − |
| |
| − | DMG-?NN-NN
| |
| − | ||| \-- PCB revision
| |
| − | ||\----- PCB descriptor MBC
| |
| − | |\------ PCB descriptor RAM/ROM size combination
| |
| − | \------- PCB code
| |
| − |
| |
| − | === PCB Code ===
| |
| − |
| |
| − | *A: Production Cartridges
| |
| − | *B: Test Cartridges
| |
| − | *Z: Revisions of certain A?? variants. Sometimes routing changes.
| |
| − |
| |
| − | === PCB Descriptor ===
| |
| − |
| |
| − | Descriptors describe MBC and ROM/RAM size combinations only.
| |
| − |
| |
| − | {| class="wikitable sortable"
| |
| − | |-
| |
| − | ! rowspan="2" |Number
| |
| − | ! scope="col" class="unsortable" rowspan="2" |MBC
| |
| − | ! scope="col" class="unsortable" colspan="2" |RAM/ROM size combination
| |
| − | |-
| |
| − | ! RAM sizes
| |
| − | ! ROM sizes
| |
| − | |-
| |
| − | | 0
| |
| − | | MBC5 (w/ or w/o rumble)
| |
| − | | 4/8M
| |
| − | | 2/4k EEPROM or 1M SRAM
| |
| − | |-
| |
| − | | 1
| |
| − | | MBC5 (w/ rumble)
| |
| − | | 16/32/64M
| |
| − | | 64k
| |
| − | |-
| |
| − | | 2
| |
| − | | G-MMC1 (+ 8M FLASH)
| |
| − | | 2/4/8M
| |
| − | | 256k
| |
| − | |-
| |
| − | | 3
| |
| − | | MBC6 (+ 8M FLASH)
| |
| − | | 16/32/64M
| |
| − | | 256k
| |
| − | |-
| |
| − | | 4
| |
| − | | MBC7
| |
| − | | 4/8M
| |
| − | | -?
| |
| − | |-
| |
| − | | 5
| |
| − | | -
| |
| − | | -?
| |
| − | | -?
| |
| − | |-
| |
| − | | 6
| |
| − | | -
| |
| − | | 2/4/8M
| |
| − | | 64k
| |
| − | |-
| |
| − | | 7
| |
| − | | -
| |
| − | | 16/32M
| |
| − | | 2/4k EEPROM
| |
| − | |-
| |
| − | | 8
| |
| − | | -
| |
| − | | -?
| |
| − | | -?
| |
| − | |-
| |
| − | | 9
| |
| − | | -
| |
| − | | -?
| |
| − | | -?
| |
| − | |}
| |
| − |
| |
| − | Maybe actually hierarchy? I.e. second figure is sub-index in first figure MBC PCB designs?
| |
| − |
| |
| − | === PCB Revisions ===
| |
| − |
| |
| − | Numbers include
| |
| − |
| |
| − | *01
| |
| − | *10
| |
| − |
| |
| − | Never observed any major differences. Maybe minor solder mask differences?
| |