ADC
Add With Carry
This opcode group adds the contents of the variable byte input and the carry flag to the contents of register A, to be stored in register A. The formula can be seen as A=A+r+CY. Since register A is an 8-bit register, you must make sure it wraps around appropriately to only contain an 8-bit value in the range of 0-0xFF (0-255).
The ADC operation code groups are known as follows:
1) ADC A, r
2) ADC A, n
3) ADC A, (HL)
Register F Flag Computation
The subtract flag bit is always reset to 0 for any ADC operation. The zero flag bit is set to 1 if the operation sets register A to 0, otherwise the zero flag is reset to 0. The carry flag bit is set to 1 if the operation causes a mathematical carry from bit 7. The half-carry flag bit is set to 1 if the operation causes a mathematical carry from bit 3.
ADC A, r
Machine Cycle Count: 1
Variable r is a CPU register as specified in the table below.
| # | Register (in place of r) |
| 8F | A |
| 88 | B |
| 89 | C |
| 8A | D |
| 8B | E |
| 8C | H |
| 8D | L |
ADC A, n
Machine Cycle Count: 2
OP Code #CE
n is the value of the byte of memory stored at the current immediate value, where the program counter is the 16-bit memory address being accessed.
ADC A, (HL)
Machine Cycle Count: 2
OP Code #8E
(HL) is the value of the byte of memory stored at the location where the address is the 16-bit value of registers H and L, where the register H is the upper byte, and register L is the lower byte.
