Endianness

The SM83 CPU core is little-endian, in which less significant bytes are stored in a lower address. This is exposed in three places:

1. Instructions with 16-bit operands, such as ld de, d16 and call a16. This is visible in self-modifying code in SRAM, WRAM, or HRAM.
2. push and pop instructions
3. ld [a16], sp ($08) instruction

The PPU has a mix of endiannesses.

• Pattern data ($8000-$97FF) is big-endian within a byte. The first bit to be sent to the LCD is the most significant bit.
• Pattern data is little-endian between bytes. The byte storing bit 0 of the color indices of the 8 pixels in each 8×1-pixel sliver is at a lower address than the byte storing bit 1.
• DMG color palette registers (BGP, OBP0, and OBP1) have the shade values for low color indices in low bits and high color indices in high bits.
• GBC color palette values written to BCPD and OCPD take bits 7-0 before bits 15-8, where green straddles bits 9-5.
• Addresses in DMA to VRAM are big-endian, with the more significant byte written to the lower address.

The APU is little-endian, with pulse and noise period bits 7-0 in a lower address than bits 10-8.

Cartridges are mostly little-endian.

• MBC1 bank number bits 4-0 are in a lower address than bits 6-5.
• MBC5 bank number bits 7-0 are in a lower address than bit 8.
• The 16-bit checksum in the ROM header at $014E is big-endian.