Difference between revisions of "LD (16-bit)"
From GbdevWiki
(Created page with 'The 2-byte immediate operand is loaded into the specified register pair. == Instructions == LD BC, $NNNN - 3 Machine Cycles LD DE, $NNNN - 3 Machine Cycles LD HL, $NNNN - 3 …') |
|||
| (One intermediate revision by the same user not shown) | |||
| Line 1: | Line 1: | ||
| + | {{Opcode}} | ||
| + | |||
The 2-byte immediate operand is loaded into the specified register pair. | The 2-byte immediate operand is loaded into the specified register pair. | ||
| Line 10: | Line 12: | ||
== Flags == | == Flags == | ||
| − | None | + | None |
Latest revision as of 11:02, 25 May 2012
This is an article about the GB-Z80 CPU.
Opcodes:
Arithmetic and logical: ADD - ADD (16-bit) including LD HL,SP+nn - ADC - AND - CP - CPL - DAA - DEC - DEC and INC (16-bit) - INC - SBC - SUB - OR - XOR
Conditional: CALL - JP - JR - RET
Load: LD (8-bit) - LD (16-bit)
Extended Set: BIT - RES - RL - RLC - RR - RRC - SET - SLA - SRA - SRL - SWAP
The 2-byte immediate operand is loaded into the specified register pair.
Instructions
LD BC, $NNNN - 3 Machine Cycles LD DE, $NNNN - 3 Machine Cycles LD HL, $NNNN - 3 Machine Cycles LD SP, $NNNN - 3 Machine Cycles
Flags
None
