Difference between revisions of "DEC and INC (16-bit)"

Latest revision as of 11:03, 25 May 2012

This is an article about the GB-Z80 CPU.

Opcodes:

Arithmetic and logical: ADD - ADD (16-bit) including LD HL,SP+nn - ADC - AND - CP - CPL - DAA - DEC - DEC and INC (16-bit) - INC - SBC - SUB - OR - XOR
Conditional: CALL - JP - JR - RET
Load: LD (8-bit) - LD (16-bit)
Extended Set: BIT - RES - RL - RLC - RR - RRC - SET - SLA - SRA - SRL - SWAP

The contents of register pair (BC, DE, HL, or SP) are incremented/decremented.

INC BC - $03 - 1 Machine Cycle
INC DE - $13 - 1 Machine Cycle
INC HL - $23 - 1 Machine Cycle
INC SP - $33 - 1 Machine Cycle

DEC BC - $0B - 1 Machine Cycle
DEC DE - $1B - 1 Machine Cycle
DEC HL - $2B - 1 Machine Cycle
DEC SP - $3B - 1 Machine Cycle

None

Revision as of 10:58, 25 May 2012 (view source) Beannaich (Talk \| contribs) ← Older edit		Latest revision as of 11:03, 25 May 2012 (view source) Beannaich (Talk \| contribs)
Line 1:		Line 1:
		+	{{Opcode}}
		+
	The contents of register pair (BC, DE, HL, or SP) are incremented/decremented.		The contents of register pair (BC, DE, HL, or SP) are incremented/decremented.