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- 11:42, 25 May 2012 (diff | hist) . . (+12) . . Template:Instruction
- 11:34, 25 May 2012 (diff | hist) . . (+136) . . N Template:Instruction (Created page with '= {{{Name}}} = {{{Description}}} == Encoding == {{{Encoding}}} == Flags == Z: {{{Z|-}}} N: {{{N|-}}} H: {{{H|-}}} C: {{{C|-}}}')
- 11:22, 25 May 2012 (diff | hist) . . (+134) . . Template:Opcode
- 11:18, 25 May 2012 (diff | hist) . . (+655) . . N BIT (Created page with '{{Opcode}} This instruction is part of the $CB prefixed extended instruction set.<br> This instruction group tests various bits of the various registers, or memory location. It …')
- 11:09, 25 May 2012 (diff | hist) . . (+8) . . ADC (current)
- 11:08, 25 May 2012 (diff | hist) . . (+184) . . ADC (→Add With Carry)
- 11:03, 25 May 2012 (diff | hist) . . (+12) . . DEC and INC (16-bit) (current)
- 11:02, 25 May 2012 (diff | hist) . . (+12) . . LD (16-bit) (current)
- 11:02, 25 May 2012 (diff | hist) . . (+1) . . LD (16-bit)
- 11:01, 25 May 2012 (diff | hist) . . (+244) . . N LD (16-bit) (Created page with 'The 2-byte immediate operand is loaded into the specified register pair. == Instructions == LD BC, $NNNN - 3 Machine Cycles LD DE, $NNNN - 3 Machine Cycles LD HL, $NNNN - 3 …')
- 10:58, 25 May 2012 (diff | hist) . . (+12) . . DEC and INC (16-bit)
- 10:58, 25 May 2012 (diff | hist) . . (+129) . . DEC and INC (16-bit)
- 10:57, 25 May 2012 (diff | hist) . . (+235) . . N DEC and INC (16-bit) (Created page with 'The contents of register pair (BC, DE, HL, or SP) are incremented. == Instructions == INC BC - $03 - 1 Machine Cycle INC DE - $13 - 1 Machine Cycle INC HL - $23 - 1 Machine …')
- 10:54, 25 May 2012 (diff | hist) . . (0) . . DEC (current)
- 10:53, 25 May 2012 (diff | hist) . . (0) . . INC (current)
- 10:08, 25 May 2012 (diff | hist) . . (+4) . . INC
- 09:33, 25 May 2012 (diff | hist) . . (+12) . . INC
- 09:30, 25 May 2012 (diff | hist) . . (+452) . . N INC (Created page with 'The byte specified by the operand is incremented. == Instructions == INC B - $04 - 1 Machine Cycle INC C - $0C - 1 Machine Cycle INC D - $14 - 1 Machine Cycle INC …')
- 09:30, 25 May 2012 (diff | hist) . . (+1) . . DEC
- 09:28, 25 May 2012 (diff | hist) . . (+4) . . DEC
- 09:26, 25 May 2012 (diff | hist) . . (+464) . . N DEC (Created page with '{{Opcode}} The byte specified by the operand is decremented. == Instructions == DEC B - $05 - 1 Machine Cycle DEC C - $0D - 1 Machine Cycle DEC D - $15 - 1 Machine…')
- 09:19, 25 May 2012 (diff | hist) . . (+12) . . XOR (current)
- 09:18, 25 May 2012 (diff | hist) . . (+12) . . OR (current)
- 09:01, 25 May 2012 (diff | hist) . . (+12) . . SUB (current)
- 09:00, 25 May 2012 (diff | hist) . . (+12) . . SBC (current)
- 08:57, 25 May 2012 (diff | hist) . . (+12) . . CPL (current)
- 08:57, 25 May 2012 (diff | hist) . . (+12) . . CP (current)
- 08:56, 25 May 2012 (diff | hist) . . (+12) . . AND (current)
- 08:55, 25 May 2012 (diff | hist) . . (+12) . . DAA (current)
- 08:46, 25 May 2012 (diff | hist) . . (-380) . . DAA
- 08:31, 25 May 2012 (diff | hist) . . (+1,368) . . N DAA (Created page with ' +---+---+---+--------------+--------------+--------------+---------+ | N | H | C | Upper Nybble | Lower Nybble | Number Added | C After | +---+---+---+--------------+---------…')
- 08:15, 25 May 2012 (diff | hist) . . (+610) . . N SBC (Created page with 'The operand, along with the Carry flag (C in the F register) is subtracted from the contents of the Accumulator, and the result is stored in the Accumulator. == Instructions == …')
- 08:13, 25 May 2012 (diff | hist) . . (+561) . . N SUB (Created page with 'The operand is subtracted from the contents of the Accumulator, and the result is stored in the Accumulator. == Instructions == SUB B - $90 - 1 Machine Cycle SUB C - $9…')
- 08:09, 25 May 2012 (diff | hist) . . (+174) . . N CPL (Created page with 'The contents of the Accumulator are inverted (one's complement). == Instructions == CPL - $2F - 1 Machine Cycle == Flags == Z: not affected N: 1 H: 1 C: not affected')
- 08:03, 25 May 2012 (diff | hist) . . (+598) . . N CP (Created page with 'The flags are updated as if a SUB instruction had been carried out. The only difference is that the Accumulator is not modified by this instruction. == Instructions == CP …')
- 07:56, 25 May 2012 (diff | hist) . . (+550) . . N OR (Created page with 'A logical OR operation is performed between the byte specified by the operand and the byte contained in the Accumulator; the result is stored in the Accumulator. == Instructions…')
- 07:52, 25 May 2012 (diff | hist) . . (+560) . . N AND (Created page with 'A logical AND operation is performed between the byte specified by the operand and the byte contained in the Accumulator; the result is stored in the Accumulator. == Instruction…')
- 07:48, 25 May 2012 (diff | hist) . . (+571) . . N XOR (Created page with 'The logical exclusive-OR operation is performed between the byte specified by the operand and the byte contained in the Accumulator; the result is stored in the Accumulator. == …')
- 07:30, 25 May 2012 (diff | hist) . . (+7) . . LD (8-bit) (current)
- 07:24, 25 May 2012 (diff | hist) . . (+31) . . Pan Docs (→Cartridges)
- 07:23, 25 May 2012 (diff | hist) . . (+41) . . Pan Docs (→Table of Contents)
- 07:20, 25 May 2012 (diff | hist) . . (+34) . . MBC1
- 07:19, 25 May 2012 (diff | hist) . . (+34) . . MBC2
- 07:18, 25 May 2012 (diff | hist) . . (+34) . . MBC3
- 07:18, 25 May 2012 (diff | hist) . . (+34) . . MBC5
- 07:16, 25 May 2012 (diff | hist) . . (+975) . . MBC5
- 07:14, 25 May 2012 (diff | hist) . . (+3,441) . . N MBC3 (Created page with '== MBC3 (max 2MByte ROM and/or 32KByte RAM and Timer) == Beside for the ability to access up to 2MB ROM (128 banks), and 32KB RAM (4 banks), the MBC3 also includes a built-in Re…')
- 07:13, 25 May 2012 (diff | hist) . . (+1,394) . . N MBC2 (Created page with '== MBC2 (max 256KByte ROM and 512x4 bits RAM) == ===0000-3FFF - ROM Bank 00 (Read Only)=== Same as for MBC1. ===4000-7FFF - ROM Bank 01-0F (Read Only)=== Same as for MBC1, but …')
- 07:10, 25 May 2012 (diff | hist) . . (+2,973) . . N MBC1 (Created page with '== MBC1 (max 2MByte ROM and/or 32KByte RAM) == This is the first MBC chip for the gameboy. Any newer MBC chips are working similiar, so that is relative easy to upgrade a progra…')
- 07:07, 25 May 2012 (diff | hist) . . (+30) . . Timer and Divider Registers (→FF04 - DIV - Divider Register (R/W))
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