BIT

This is an article about the GB-Z80 CPU.

Opcodes:

Arithmetic and logical: ADD - ADD (16-bit) including LD HL,SP+nn - ADC - AND - CP - CPL - DAA - DEC - DEC and INC (16-bit) - INC - SBC - SUB - OR - XOR
Conditional: CALL - JP - JR - RET
Load: LD (8-bit) - LD (16-bit)
Extended Set: BIT - RES - RL - RLC - RR - RRC - SET - SLA - SRA - SRL - SWAP

This instruction group tests various bits of the various registers, or memory location.

Encoding

01bbbrrr

r: Register
b: Bit to test

Where register is one of the following:

000: B    - 2 Machine Cycles
001: C    - 2 Machine Cycles
010: D    - 2 Machine Cycles
011: E    - 2 Machine Cycles
100: H    - 2 Machine Cycles
101: L    - 2 Machine Cycles
110: (HL) - 3 Machine Cycles
111: A    - 2 Machine Cycles

Flags

Z: 1 if specified bit is 0; 0 otherwise
N: 0
H: 1